module top_module (
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output [3:0] q);

	reg [3:0]data_r=4'b0000;
	always@(posedge clk)begin
		if(shift_ena)begin
			data_r[0]<=data;
			data_r[1]<=data_r[0];
			data_r[2]<=data_r[1];
			data_r[3]<=data_r[2];
		end
		else if(count_ena)begin
			if(data_r>4'b0000)
				data_r<=data_r-4'b0001;
			else
				data_r<=4'b1111;
		end
		else begin
			data_r<=data_r;
		end
	end
	assign q=data_r;
endmodule